Semiconductor memory devices including dynamic random access memory (DRAM) devices adopt a redundancy technique, which may replace defective memory cells with redundant memory cells so as to improve the yield. The redundancy techniques may be divided into two types, row redundancy and column redundancy, both of or one of which can be applied to semiconductor memory devices.
These redundancy techniques are known to those skilled in the art and at least one of these techniques is disclosed in Korean Patent Publication No. 1999-061991 entitled “Semiconductor Device Having A Plurality of Redundancy Input/Output Lines,” Korean Patent Publication No. 1998-040822 entitled “Semiconductor Memory Device Having Row Defect Repairing Circuit,” Korean Patent Publication No. 1999-073672 entitled “Column Redundancy Circuit for Use in Semiconductor Memory Devices,” U.S. Pat. No. 5,892,719 entitled “Redundancy Circuit Technique Applied DRAM of Multi-bit I/O Having Overlaid-DQ Bus,” U.S. Pat. No. 5,812,466 entitled “Column Redundancy Circuit for A Semiconductor Memory Device,” and U.S. Pat. No. 5,761,138 entitled “Memory Devices Having A Flexible Redundant Block Architecture.”
FIG. 1 is a diagram illustrating an input/output line scheme in which when one column selection line is activated, and 8-bit data is read out from one memory block. Referring to FIG. 1, a memory block BLK comprises memory cells (denoted by “●” in the memory block) which are arranged in a matrix of rows (or word lines) and columns (or bit lines). Some of the columns of the memory block are selectively coupled to input/output lines IO0-IO3 via a sense amplification and input/output block 12, which is disposed at a top of the memory block. The rest of the columns are selectively coupled to input/output lines IO4-IO7 via a sense amplification and input/output block 13, which is disposed at a bottom of the memory block BLK. Although not shown in the drawings, each of the sense amplification and input/output blocks 12 and 13 includes a latch-type sense amplifier circuit and an input/output gate circuit as is known to those skilled in the art.
In the input/output line scheme as illustrated in FIG. 1, the input/output gate circuits of the sense amplification and input/output blocks 12 and 13 are controlled in common by one column selection signal CSLj. That is, when one column selection signal CSLj is activated according to column address information, 8 columns are respectively connected to input/output lines IO0-IO7 via the sense amplification and input/output blocks 12 and 13. Consequently, when one column selection signal is activated, 8-bit data is read out from the memory block BLK or written into the memory block BLK. When a column address is inputted, one column selection line CSLj is activated.
However, as the memory blocks increase in number, the input/output line scheme of FIG. 1 becomes inadequate for laying out the input/output lines. That is, because corresponding input/output lines are disposed in each memory block and are embodied using metal, it becomes very difficult to dispose enough input/output lines in a space between adjacent memory blocks.
To solve the foregoing problem, an input/output line scheme as illustrated in FIG. 2 has been proposed. Referring to FIG. 2, four input/output lines IO0, IO2, IO4, and IO6 are disposed at a top of the memory block BLK, and four input/output lines IO1, IO3, IO5, and IO7 are disposed at a bottom of the memory block BLK. Two input/output lines IO0 and IO2 of the input/output lines IO0, IO2, IO4, and IO6 that are disposed at the top are formed at the same layer as other input/output lines IO4 and IO6. Two input/output lines IO1 and IO3 of the input/output lines IO1, IO3, IO5, and IO7 that are disposed at the bottom are formed at the same layer as other input/output lines IO5 and IO7. In the input/output line scheme, the sense amplification and input/output blocks 12 and 13, which are disposed at the top and bottom, respectively, are controlled by corresponding column selection is signals CSLjR and CSLjL, respectively. For example, when the column selection signal CSLjL is activated, the input/output lines IO0-IO3 are respectively connected to corresponding columns. Also, when the column selection signal CSLjR is activated, the input/output lines IO4-IO7 are respectively connected to corresponding columns. Here, the column selection signals CSLjR and CSLjL are activated by the identical column address information. That is, when a column address is inputted, two column selection lines CSLjR and CSLjL are simultaneously activated. However, when a defective column is replaced in a semiconductor memory device adopting the input/output line scheme of FIG. 2, there arises a problem, which will be described in detail hereinafter.
FIG. 3 is a block diagram-of a conventional semiconductor memory device. As illustrated in FIG. 3, an input/output line scheme of FIG. 3 is the same as that of FIG. 2 and descriptions thereof will be omitted for brevity. The semiconductor memory device comprises a redundant memory block RBLK and redundant sense amplification and input/output blocks 14 and 15. The redundant sense amplification and input/output block 14 disposed at a top of the memory block RBLK selectively connects a part of redundant columns of the redundant memory block to redundant input/output lines RIO0 and RIO1, in response to a redundancy column selection signal RCSLj. Likewise, the redundant sense amplification and input/output block 15 disposed at a bottom of the memory block RBLK selectively connects the rest of the redundant columns to redundant input/output lines RIO2 and RIO3, in response to the redundancy column selection signal RCSLj. That is, when currently inputted column address information includes an address of a defective cell, one redundant column selection signal RCSLj is activated. Consequently, four columns are replaced at one time.
When any row is selected, input/output lines IO0-IO7 of the memory block BLK are respectively coupled to selectors SEL0-SEL7. At this time, signals of redundant input/output lines RIO0-RIO3 are respectively supplied to a first group of selectors SEL0-SEL3 and simultaneously to a second group of selectors SEL5-SEL8. In the case that the column address information includes defective information, the first or second group of selectors select the redundant input/output lines rather than the input/output lines of the memory block. For example, when defective cells are connected to the input/output lines IO0-IO3 related to the column selection signal CSLjL, the first group of selectors SEL0-SEL3 select the redundant input/output lines RIO0-RI03 rather than the input/output lines IO0-IO3. Alternatively, when defective cells are connected to the input/output lines IO4-IO7 related to the column selection signal CSLjR, the second group of selectors SEL4-SEL7 select the redundant input/output lines RIO0-RI03 rather than the input/output lines IO4-IO7. The foregoing repairing method is normally called a “data line redundancy.”
A problem of the semiconductor memory device with the foregoing data line redundancy scheme is that when columns activated by each of the column selection signals CSLjR and CSLjL include defective data bit(s), the semiconductor memory device cannot perform a repair operation. This is because the redundancy input/output lines RIO0-RI03 are shared by the selectors of each group. Only the input/output lines IO0-IO3 or IO4-IO7, which are selected by one of the simultaneously activated column selection signals CSLjR and CSLjL, may be replaced by the redundancy input/output lines RIO0-RI03 via the first or second group of selectors SEL0-SEL3 or SEL4-SEL7.